The standard framing of GPU generations focuses on compute: TFLOPS, tensor core counts, HBM capacity. None of that determines fabric architecture. What determines fabric architecture is the interconnect stack that ships with the GPU.

Three parameters change with every generation and cascade into infrastructure decisions:

Intra-node bandwidth: how fast can a GPU communicate with its siblings inside the same DGX node? This is NVLink territory. Higher NVLink bandwidth means larger batch sizes can be processed with tensor parallelism inside a single node, reducing the amount of inter-node AllReduce traffic that has to cross the fabric. The network engineer's job gets easier as NVLink bandwidth grows -- fewer jobs need inter-node scale-out for a given model size.

PCIe interface bandwidth: how fast can the GPU talk to the host CPU and to PCIe-attached NICs? This is the binding constraint for any GPU that isn't in an SXM form factor. A 400 Gbps ConnectX-7 in PCIe Gen 4 is already close to the one-directional PCIe ceiling. Gen 5 doubles the ceiling, but the ceiling still exists and still matters.

NVLink Switch support: not all GPUs can participate in an external NVLink Switch fabric. Only SXM-form-factor GPUs have the full NVLink port count required. PCIe-form-factor GPUs either have no NVLink or a reduced implementation. This is the form factor choice that determines whether a GPU can join a scale-up NVLink cluster at all.