The calculations from Acts 2-6 combine into a topology sizing workflow. An engineer given a set of requirements (number of nodes, required AllReduce bandwidth, budget) follows this sequence:

Step 1: Calculate NIC bandwidth Total NIC bandwidth = node count x NICs per node x NIC speed

For 128 DGX H100 nodes: 128 x 8 x 400G = 409.6 Tb/s

Step 2: Choose target oversubscription For AI training: 1:1 (non-blocking). For mixed workloads: up to 2:1.

Step 3: Calculate required fabric bandwidth At 1:1: fabric must carry 409.6 Tb/s. Bisection must carry 204.8 Tb/s.

Step 4: Choose switch radix and calculate stage count With 64-port switches (32 downlinks, 32 uplinks per leaf):

• 128 nodes x 8 NICs = 1,024 NIC connections
• At 32 downlinks per leaf: 1,024 / 32 = 32 leaf switches
• 32 leaf switches x 32 uplinks = 1,024 uplinks to spine
• At 32 ports per spine switch (all uplinks): 1,024 / 32 = 32 spine switches
• This is a 2-stage design (32 leaf + 32 spine = 64 switches)

Check non-blocking:

• Each leaf: 32 downlinks x 400G = 12.8 Tb/s downlink
• Each leaf: 32 uplinks x 400G = 12.8 Tb/s uplink
• 1:1 -> non-blocking [ok]

Step 5: Calculate AllReduce hop count 2-stage (leaf-spine): 2 hops (DGX -> Leaf -> Spine -> Leaf -> DGX) = 4 total traversals = 2 round trips

Step 6: Verify with buffer calculation 32-node AllReduce burst per rail: 32 x 400G x 1ms = 1.6 Gb = 200 MB needed per switch Spectrum-X SN5600 shared buffer: 64 MB -- tight but manageable with per-packet load balancing distributing the burst across multiple uplinks.

The 128-node BasePOD conclusion: A 2-stage, 64-port switch, non-blocking design with Spectrum-X SN5600 supports full AllReduce at line rate with adequate buffer headroom when RSHP is enabled.