Before we talk about cables, form factors, and connectors, we need to understand the signal processing chain inside the switch. This chain explains why optics are expensive, why CPO exists, and what actually fails when a transceiver error count starts climbing.

When a 400G signal arrives at a switch port, this is what happens:

1. The pluggable module receives the signal

The OSFP transceiver sitting in the switch faceplate cage receives either optical signals (from fiber) or electrical signals (from copper DAC). If optical, the transceiver converts photons to electrical signals internally.

2. The demultiplexer splits the signal into lanes

400G does not arrive as a single 400G stream. It arrives as multiple lanes running in parallel -- for example, eight lanes at 50 Gbps each, or four lanes at 100 Gbps each. A demultiplexer (demux) separates the incoming signal into these individual lanes and routes each one to a dedicated DSP input.

3. The DSP processes each lane

The Digital Signal Processor is the intelligence inside the transceiver. It performs four critical functions on each lane:

Demodulation: interprets the voltage levels in the incoming PAM-4 signal and converts them to binary bits. A PAM-4 signal uses four voltage levels to represent two bits per symbol -- the DSP must precisely distinguish between them despite noise accumulated over the cable run.

Forward Error Correction (FEC): checks and corrects bit errors introduced during transmission. At 400G and above, FEC is mandatory -- the raw bit error rate of PAM-4 over typical cable runs is too high for reliable communication without correction. Common algorithms are RS-FEC (Reed-Solomon) and LDPC (Low-Density Parity-Check). FEC adds approximately 100 nanoseconds of latency per hop -- a cost that is paid on every link in every AllReduce path.

Clock Data Recovery (CDR): extracts timing information from the incoming data stream and uses it to precisely sample each bit. At 400G speeds, the timing window for sampling each bit is measured in picoseconds. CDR is what prevents accumulated timing drift from causing cascading errors.

Equalization: compensates for signal distortion caused by the cable and connector. Cables have frequency-dependent attenuation -- high-frequency components of the signal travel slower and attenuate more than low-frequency components. Two equalization techniques are used: FFE (feed-forward equalization) pre-compensates the transmitted signal before it enters the cable, and DFE (decision-feedback equalization) post-corrects the received signal using knowledge of previously decoded symbols.

4. The SerDes bridges the transceiver to the switch ASIC

After the DSP has decoded each lane into clean binary data, the Serializer/ Deserializer (SerDes) on the switch ASIC handles the final conversion between the DSP's output and the ASIC's internal data bus. The switch ASIC processes data in wide parallel words internally but communicates over high-speed serial lanes with the transceiver.

5. The packet forwarding engine processes the packet

Once the SerDes has assembled the bits into frames, the PFE can parse the Ethernet or InfiniBand packet, look up the destination, and forward it.

The entire chain runs in reverse for transmitted packets: PFE -> SerDes -> DSP (modulation, FEC encoding, equalization) -> multiplexer (combines lanes) -> pluggable module (converts to optical or electrical) -> cable.

The cost of this chain

The DSP is the dominant cost centre. It consumes approximately 20-40% of the bill of materials for a pluggable module and roughly 50% of the module's power dissipation. A 400G QSFP-DD module draws 3-4 watts in total -- the DSP accounts for 1.5-2 watts of that. An 800G OSFP module draws 12-15 watts.

This cost structure explains why three disruptive technologies -- CPO, LPO, and LRO -- are entering the market. Each one moves some or all DSP function out of the pluggable module and into the switch ASIC, which is already cooled by the same heatsink. We return to this in Act 9.